The present application relates to semiconductor technology, and more particularly to a FinFET device containing unmerged source/drain regions and a method in which an etch stop structure is used to protect the unmerged source/drain regions during formation of contact metal structures.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar field effect transistors.
In such semiconductor FinFET devices, the source region and the drain region are typically formed by growing an epitaxial semiconductor material from the exposed surfaces of the semiconductor material fin not protected by a gate structure and a gate spacer. Processes are known for providing merged source regions and merged drain regions. Such processes are however not suitable for 10 nm and beyond devices.
Processes for providing unmerged source regions and unmerged drain regions are also known which can be used for providing 10 nm and beyond devices. Prior art processes of providing unmerged source regions and unmerged drain regions however have several drawbacks/challenges associated therewith. For example, prior art processes of providing unmerged source regions and unmerged drain regions can exhibit a high external resistance, Rext, due to a reduced contact area, and/or a variability of contact height and/or nitride liner consumption during a contact reactive ion etch (RIE) and/or a risk of over-consumption of the epitaxial semiconductor material used to provide the unmerged source/drain regions during a RIE process and/or a metal semiconductor alloy (i.e., silicide) punchthrough in the source/drain regions leading to increased gate to drain leakage.
In view of the above, there is a continued need to provide a method of forming unmerged source/drain regions for finFET devices which avoids at least one of the drawbacks/challenges mentioned above for prior art processes of providing unmerged source/drain regions.